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MC10EP016, MC100EP016 3.3V / 5V ECL 8-Bit Synchronous Binary Up Counter
The MC10/100EP016 is a high-speed synchronous, presettable, cascadeable 8-bit binary counter. Architecture and operation are the same as the MC10E016 in the ECLinPSTM family. The counter features internal feedback to TC gated by the TCLD (Terminal Count Load) pin. When TCLD is LOW (or left open, in which case it is pulled LOW by the internal pulldowns), the TC feedback is disabled, and counting proceeds continuously, with TC going LOW to indicate an all-one state. When TCLD is HIGH, the TC feedback causes the counter to automatically reload upon TC = LOW, thus functioning as a programmable counter. The Qn outputs do not need to be terminated for the count function to operate properly. To minimize noise and power, unused Q outputs should be left unterminated. COUT and COUT provide differential outputs from a single, non-cascaded counter or divider application. COUT and COUT should not be used in cascade configuration. Only TC should be used for a counter or divider cascade chain output. A differential clock input has also been added to improve performance. The 100 Series contains temperature compensation.
http://onsemi.com MARKING DIAGRAM*
LQFP-32 FA SUFFIX CASE 873A
MCxxx EP016 AWLYYWW 32 1
xxx A WL YY WW
= 10 OR 100 = Assembly Location = Wafer Lot = Year = Work Week
* 500 ps Typical Propagation Delay * PECL Mode Operating Range: VCC = 3.0 V to 5.5 V * * * * * * * * * *
with VEE = 0 V NECL Mode Operating Range: VCC = 0 V with VEE = -3.0 V to -5.5 V Open Input Default State Safety Clamp on Inputs Internal TC Feedback (Gated) Addition of COUT and COUT 8-Bit Differential Clock Input VBB Output Fully Synchronous Counting and TC Generation Asynchronous Master Reset
*For additional information, see Application Note AND8002/D
ORDERING INFORMATION
Device MC10EP016FA MC10EP016FAR2 MC100EP016FA MC100EP016FAR2 Package LQFP-32 Shipping 250 Units/Tray
LQFP-32 2000 Tape & Reel LQFP-32 250 Units/Tray
LQFP-32 2000 Tape & Reel
(c) Semiconductor Components Industries, LLC, 2002
1
September, 2002 - Rev. 10
Publication Order Number: MC10EP016/D
MC10EP016, MC100EP016
VBB CLK CLK P0 P1 P2 P3 P4
24 PE CE MR VEE Q0 Q1 Q2 VCC 25 26 27 28 29 30 31 32 1
23
22
21
20
19
18
17 16 15 14 P5 P6 P7 VCC TC COUT
PIN DESCRIPTION
PIN P0-P7* Q0-Q7 CE* PE* MR* CLK*, CLK* TC FUNCTION ECL Parallel Data (Preset) Inputs ECL Data Outputs ECL Count Enable Control Input ECL Parallel Load Enable Control Input ECL Master Reset ECL Differential Clock ECL Terminal Count Output ECL TC-Load Control Input ECL Differential Output Positive Supply Negative Supply Reference Voltage Output
MC10EP016 MC100EP016
13 12 11 10 9
TCLD* COUT COUT, COUT VEE VCC VEE VBB
2
3
4
5
6
7
8
* Pins will default LOW when left open. VCC Q3 Q4 Q5 Q6 Q7 TCLD VCC
Warning: All VCC and VEE pins must be externally connected to Power Supply to guarantee proper operation.
Figure 1. 32-Lead LQFP Pinout (Top View) FUNCTION TABLES
CE X L L H X X PE L H H H X X TCLD MR X L H X X X L L L L L H CLK Z Z Z Z ZZ X FUNCTION Load Parallel (Pn to Qn) Continuous Count Count; Load Parallel on TC = LOW Hold Masters Respond, Slaves Hold Reset (Qn : = LOW, TC : = HIGH)
ZZ = Clock Pulse (High-to-Low) Z = Clock Pulse (Low-to-High)
FUNCTION TABLE
Function Load Count PE L H H H H L H H H H H H H H X CE X L L L L X H H L L L L L L X MR L L L L L L L L L L L L L L H TCLD X L L L L X X X H H H H H H X CLK Z Z Z Z Z Z Z Z Z Z Z Z Z Z X P7-P4 H X X X X H X X H H H H H H X P3 H X X X X H X X L L L L L L X P2 H X X X X H X X H H H H H H X P1 L X X X X L X X H H H H H H X P0 L X X X X L X X L L L L L L X Q7-Q4 H H H H L H H H H H H H H H L Q3 H H H H L H H H H H H L L H L Q2 H H H H L H H H H H H H H L L Q1 L L H H L L L L L H H H H L L Q0 L H L H L L L L H L H L H L L TC H H H L H H H H H H L H H H H COUT H H H L H H H H H H L H H H H COUT L L L H L L L L L L H L L L L
Load Hold
Load on Terminal Count
Reset
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MC10EP016, MC100EP016
Q0 PE TCLD Q1 Q7
Q0M CE BIT 0 P0 P1 MASTER Q0M SLAVE Q0 CE BIT 1
CE Q Q1 0 Q2 Q3 Q4 Q5 Q
6
BIT 7
P7
MR CLK
CLK
BITS 2-6
TC
5
VBB VEE
COUT COUT
Note that this diagram is provided for understanding of logic operation only. It should not be used for propagation delays as many gate functions are achieved internally without incurring a full gate delay.
Figure 2. 8-BIT Binary Counter Logic Diagram
ATTRIBUTES
Characteristics Internal Input Pulldown Resistor Internal Input Pullup Resistor ESD Protection Human Body Model Machine Model Charged Device Model Value 75 kW N/A > 2 kV > 100 V > 2 kV Level 2 Oxygen Index: 28 to 34 UL 94 V-0 @ 0.125 in 897 Devices
Moisture Sensitivity (Note 1) Flammability Rating Transistor Count Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see Application Note AND8003/D.
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MC10EP016, MC100EP016
MAXIMUM RATINGS (Note 2)
Symbol VCC VEE VI Iout IBB TA Tstg JA JC Parameter PECL Mode Power Supply NECL Mode Power Supply PECL Mode In ut Voltage Input NECL Mode Input Voltage Output Current VBB Sink/Source Operating Temperature Range Storage Temperature Range Thermal Resistance (Junction-to-Ambient) Thermal Resistance (Junction-to-Case) 0 LFPM 500 LFPM std bd 32 LQFP 32 LQFP 32 LQFP Condition 1 VEE = 0 V VCC = 0 V VEE = 0 V VCC = 0 V Continuous Surge VI VCC VI VEE Condition 2 Rating 6 -6 6 -6 50 100 0.5 -40 to +85 -65 to +150 80 55 12 to 17 265 Units V V V V mA mA mA C C C/W C/W C/W C
Tsol Wave Solder <2 to 3 sec @ 248C 2. Maximum Ratings are those values beyond which device damage may occur.
10EP DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 3)
-40C Symbol IEE VOH VOL VIH VIL VBB VIHCMR IIH IIL Characteristic Power Supply Current Output HIGH Voltage (Note 4) Output LOW Voltage (Note 4) Input HIGH Voltage (Single-Ended) Input LOW Voltage (Single-Ended) Output Voltage Reference Input HIGH Voltage Common Mode Range (Differential) (Note 5) Input HIGH Current Input LOW Current 0.5 Min 120 2165 1365 2090 1365 1790 2.0 1890 Typ 160 2290 1490 Max 200 2415 1615 2415 1690 1990 3.3 150 0.5 Min 120 2230 1430 2155 1460 1855 2.0 1955 25C Typ 160 2355 1555 Max 200 2480 1680 2480 1755 2055 3.3 150 0.5 Min 120 2290 1490 2215 1490 1915 2.0 2015 85C Typ 160 2415 1615 Max 200 2540 1740 2540 1815 2115 3.3 150 Unit mA mV mV mV mV mV V A A
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 3. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to -2.2 V. 4. All loading with 50 W to VCC-2.0 volts. 5. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. 10EP DC CHARACTERISTICS, PECL VCC = 5.0 V, VEE = 0 V (Note 6) -40C Symbol IEE VOH VOL VIH VIL VBB VIHCMR IIH IIL Characteristic Power Supply Current (Note 7) Output HIGH Voltage (Note 8) Output LOW Voltage (Note 8) Input HIGH Voltage (Single-Ended) Input LOW Voltage (Single-Ended) Output Voltage Reference Input HIGH Voltage Common Mode Range (Differential) (Note 9) Input HIGH Current Input LOW Current 0.5 Min 120 3865 3065 3790 3065 3490 2.0 3590 Typ 160 3990 3190 Max 200 4115 3315 4115 3390 3690 5.0 150 0.5 Min 120 3930 3130 3855 3130 3555 2.0 3655 25C Typ 160 4055 3255 Max 200 4180 3380 4180 3455 3755 5.0 150 0.5 Min 120 3990 3190 3915 3190 3615 2.0 3715 85C Typ 160 4115 3315 Max 200 4240 3440 4240 3515 3815 5.0 150 Unit mA mV mV mV mV mV V A A
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 6. Input and output parameters vary 1:1 with VCC. VEE can vary +2.0 V to -0.5 V. 7. Required 500 lfpm air flow when using +5 V power supply. For (VCC - VEE) >3.3 V, 5 W to 10 W in line with VEE required for maximum thermal protection at elevated temperatures. Recommend VCC-VEE operation at 3.3 V. 8. All loading with 50 W to VCC-2.0 volts. 9. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal.
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MC10EP016, MC100EP016
10EP DC CHARACTERISTICS, NECL VCC = 0 V, VEE = -5.5 V to -3.0 V (Note 10)
-40C Symbol IEE VOH VOL VIH VIL VBB VIHCMR IIH Characteristic Power Supply Current (Note 11) Output HIGH Voltage (Note 12) Output LOW Voltage (Note 12) Input HIGH Voltage (Single-Ended) Input LOW Voltage (Single-Ended) Output Voltage Reference Input HIGH Voltage Common Mode Range (Differential) (Note 13) Input HIGH Current Min 120 -1135 -1935 -1210 -1935 -1510 -1410 VEE+2.0 Typ 160 -1010 -1810 Max 200 -885 -1685 -885 -1610 -1310 0.0 150 Min 120 -1070 -1870 -1145 -1870 -1445 -1345 VEE+2.0 25C Typ 160 -945 -1745 Max 200 -820 -1620 -820 -1545 -1245 0.0 150 Min 120 -1010 -1810 -1085 -1810 -1385 -1285 VEE+2.0 85C Typ 160 -885 -1685 Max 200 -760 -1560 -760 -1485 -1185 0.0 150 Unit mA mV mV mV mV mV V A
IIL Input LOW Current 0.5 0.5 0.5 A NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 10. Input and output parameters vary 1:1 with VCC. 11. Required 500 lfpm air flow when using -5 V power supply. For (VCC - VEE) >3.3 V, 5 W to 10 W in line with VEE required for maximum thermal protection at elevated temperatures. Recommend VCC-VEE operation at 3.3 V. 12. All loading with 50 W to VCC-2.0 volts. 13. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. 100EP DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 14) Symbol IEE VOH VOL VIH VIL VBB VIHCMR IIH IIL Characteristic Power Supply Current Output HIGH Voltage (Note 15) Output LOW Voltage (Note 15) Input HIGH Voltage (Single-Ended) Input LOW Voltage (Single-Ended) Output Voltage Reference Input HIGH Voltage Common Mode Range (Differential) (Note 16) Input HIGH Current Input LOW Current 0.5 Min 120 2155 1355 2075 1355 1775 2.0 1875 -40C Typ 160 2280 1480 Max 200 2405 1605 2420 1675 1975 3.3 150 0.5 Min 120 2155 1355 2075 1355 1775 2.0 1875 25C Typ 160 2280 1480 Max 200 2405 1605 2420 1675 1975 3.3 150 0.5 Min 120 2155 1355 2075 1355 1775 2.0 1875 85C Typ 160 2280 1480 Max 200 2405 1605 2420 1675 1975 3.3 150 Unit mA mV mV mV mV mV V A A
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 14. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to -2.2 V. 15. All loading with 50 W to VCC-2.0 volts. 16. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. 100EP DC CHARACTERISTICS, PECL VCC = 5.0 V, VEE = 0 V (Note 17) -40C Symbol IEE VOH VOL VIH VIL VBB VIHCMR IIH IIL Characteristic Power Supply Current (Note 18) Output HIGH Voltage (Note 19) Output LOW Voltage (Note 19) Input HIGH Voltage (Single-Ended) Input LOW Voltage (Single-Ended) Output Voltage Reference Input HIGH Voltage Common Mode Range (Differential) (Note 20) Input HIGH Current Input LOW Current 0.5 Min 120 3855 3055 3775 3055 3475 2.0 3575 Typ 160 3980 3180 Max 200 4105 3305 4120 3375 3675 5.0 150 0.5 Min 120 3855 3055 3775 3055 3475 2.0 3575 25C Typ 160 3980 3180 Max 200 4105 3305 4120 3375 3675 5.0 150 0.5 Min 120 3855 3055 3775 3055 3475 2.0 3575 85C Typ 160 3980 3180 Max 200 4105 3305 4120 3375 3675 5.0 150 Unit mA mV mV mV mV mV V A A
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 17. Input and output parameters vary 1:1 with VCC. VEE can vary +2.0 V to -0.5 V. 18. Required 500 lfpm air flow when using +5 V power supply. For (VCC - VEE) >3.3 V, 5 W to 10 W in line with VEE required for maximum thermal protection at elevated temperatures. Recommend VCC-VEE operation at 3.3 V. 19. All loading with 50 W to VCC-2.0 volts. 20. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal.
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MC10EP016, MC100EP016
100EP DC CHARACTERISTICS, NECL VCC = 0 V, VEE = -5.5 V to -3.0 V (Note 21)
-40C Symbol IEE VOH VOL VIH VIL VBB VIHCMR IIH IIL Characteristic Power Supply Current (Note 22) Output HIGH Voltage (Note 23) Output LOW Voltage (Note 23) Input HIGH Voltage (Single-Ended) Input LOW Voltage (Single-Ended) Output Voltage Reference Input HIGH Voltage Common Mode Range (Differential) (Note 24) Input HIGH Current Input LOW Current 0.5 Min 120 -1145 -1945 -1225 -1945 -1525 -1425 Typ 160 -1020 -1820 Max 200 -895 -1695 -880 -1625 -1325 0.0 150 0.5 Min 120 -1145 -1945 -1225 -1945 -1525 -1425 25C Typ 160 -1020 -1820 Max 200 -895 -1695 -880 -1625 -1325 0.0 150 0.5 Min 120 -1145 -1945 -1225 -1945 -1525 -1425 85C Typ 160 -1020 -1820 Max 200 -895 -1695 -880 -1625 -1325 0.0 150 Unit mA mV mV mV mV mV V A A
VEE+2.0
VEE+2.0
VEE+2.0
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 21. Input and output parameters vary 1:1 with VCC. 22. Required 500 lfpm air flow when using -5 V power supply. For (VCC - VEE) >3.3 V, 5 W to 10 W in line with VEE required for maximum thermal protection at elevated temperatures. Recommend VCC-VEE operation at 3.3 V. 23. All loading with 50 W to VCC-2.0 volts. 24. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal.
AC CHARACTERISTICS VEE = -3.0 V to -5.5 V; VCC = 0 V or VCC = 3.0 V to 5.5 V; VEE = 0 V (Note 25)
-40C Symbol fCOUNT Characteristic Maximum Frequency Q, TC COUT/COUT tPLH tPHL Propagation Delay (10) (10) (10) (10) (10) (10) (100) (100) (100) (100) (100) (100) Setup Time CLK to Q MR to Q CLK to TC MR to TC CLK to COUT MR to COUT CLK to Q MR to Q CLK to TC MR to TC CLK to COUT MR to COUT Pn CE PE TCLD Pn CE PE TCLD 300 300 350 250 400 300 350 400 350 400 400 450 100 500 500 500 100 500 500 500 >1 > 800 460 400 420 350 470 400 500 550 500 550 550 600 -50 300 300 300 -50 300 300 300 2.6 200 550 120 80 300 210 320 8.5 200 550 120 600 500 550 450 650 550 650 700 650 700 750 800 350 400 400 350 450 400 400 450 400 450 450 500 100 500 500 500 100 500 500 500 >1 > 800 500 500 500 450 550 500 550 590 550 590 600 640 -50 300 300 300 -50 300 300 300 2.5 80 300 220 320 8.0 200 550 150 650 600 600 550 700 650 700 750 700 750 800 850 400 450 400 400 450 450 480 520 480 520 530 570 100 500 500 500 100 500 500 500 >1 > 800 560 580 550 510 600 560 630 670 630 670 680 720 -50 300 300 300 -50 300 300 300 2.5 80 300 250 450 8.0 700 700 700 600 800 700 780 820 780 820 880 920 GHz MHz ps Min Typ Max Min 25C Typ Max Min 85C Typ Max Unit
tS
ps
tH
Hold Time
ps
tJITTER tRR tPW tr tf
Clock Random Jitter (RMS >1000 Waveforms) Reset Recovery Time Minimum Pulse Width CLK, MR Output Rise/Fall Times 20% - 80%
ps ps ps ps
25. Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 W to VCC-2.0 V.
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MC10EP016, MC100EP016 Applications Information
Cascading Multiple EP016 Devices For applications which call for larger than 8-bit counters multiple EP016s can be tied together to achieve very wide bit width counters. The active low terminal count (TC) output and count enable input (CE) greatly facilitate the cascading of EP016 devices. Two EP016s can be cascaded without the need for external gating, however for counters wider than 16 bits external OR gates are necessary for cascade implementations. Figure 3 below pictorially illustrates the cascading of 4 EP016s to build a 32-bit high frequency counter. Note the EP01 gates used to OR the terminal count outputs of the lower order EP016s to control the counting operation of the higher order bits. When the terminal count of the preceding device (or devices) goes low (the counter reaches an all 1s state) the more significant EP016 is set in its count mode and will count one binary digit upon the next positive clock transition. In addition, the preceding devices will also count one bit thus sending their terminal count outputs back to a high state disabling the count operation of the more significant counters and placing them back into hold modes. Therefore, for an EP016 in the chain to count, all of the lower order terminal count outputs must be in the low state. The bit width of the counter can be increased or decreased by simply adding or subtracting EP016 devices from Figure 3 and maintaining the logic pattern illustrated in the same figure. The maximum frequency of operation for a cascaded counter chain is set by the propagation delay of the TC output, the necessary setup time of the CE input, and the propagation delay through the OR gate controlling it (for 16-bit counters the limitation is only the TC propagation delay and the CE setup time). Figure 3 shows EP01 gates used to control the count enable inputs, however, if the frequency of operation is slow enough, a LVECL OR gate can be used. Using the worst case guarantees for these parameters.
LOAD Q0 to Q7 Q0 to Q7 Q0 to Q7 Q0 to Q7
LO
CE
PE EP016 LSB
CE
PE EP016
CE
PE EP016
CE
PE
EP016 MSB CLK CLK
EP01
CLK CLK
TC
CLK CLK
TC
EP01
CLK CLK
TC
TC
P0 to P7 CLK CLK
P0 to P7
P0 to P7
P0 to P7
Figure 3. 32-Bit Cascaded EP016 Counter
Note that this assumes the trace delay between the TC outputs and the CE inputs are negligible. If this is not the case estimates of these delays need to be added to the calculations. Programmable Divider The EP016 has been designed with a control pin which makes it ideal for use as an 8-bit programmable divider. The
TCLD pin (load on terminal count) when asserted reloads the data present at the parallel input pin (Pn's) upon reaching terminal count (an all 1s state on the outputs). Because this feedback is built internal to the chip, the programmable division operation will run at very nearly the same frequency as the maximum counting frequency of the device. Figure 4 below illustrates the input conditions necessary for utilizing the EP016 as a programmable divider set up to divide by 113.
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MC10EP016, MC100EP016 Applications Information (continued)
H L L L P4 H P3 H H H
Table 1. Preset Values for Various Divide Ratios
Divide de Ratio 2 3 4 5 * * 112 113 114 * * 254 255 256 P7 H H H H * * H H H * * L L L P6 H H H H * * L L L * * L L L Preset Data Inputs P5 H H H H * * L L L * * L L L P4 H H H H * * H L L * * L L L P3 H H H H * * L H H * * L L L P2 H H H L * * L H H * * L L L P1 H L L H * * L H H * * H L L P0 L H L H * * L H L * * L H L
P7 P6 P5 H L H PE CE TCLD CLK CLK Q7 Q6 Q5
P2 P1 P0
TC COUT COUT Q4 Q3 Q2 Q1 Q0
Figure 4. Mod 2 to 256 Programmable Divider
To determine what value to load into the device to accomplish the desired division, the designer simply subtracts the binary equivalent of the desired divide ratio from the binary value for 256. As an example for a divide ratio of 113: Pn's = 256 - 113 = 8F16 = 1000 1111 where: P0 = LSB and P7 = MSB Forcing this input condition as per the setup in Figure 4 will result in the waveforms of Figure 5. Note that the TC output is used as the divide output and the pulse duration is equal to a full clock period. For even divide ratios, twice the desired divide ratio can be loaded into the EP016 and the TC output can feed the clock input of a toggle flip flop to create a signal divided as desired with a 50% duty cycle.
A single EP016 can be used to divide by any ratio from 2 to 256 inclusive. If divide ratios of greater than 256 are needed multiple EP016s can be cascaded in a manner similar to that already discussed. When EP016s are cascaded to build larger dividers the TCLD pin will no longer provide a means for loading on terminal count. Because one does not want to reload the counters until all of the devices in the chain have reached terminal count, external gating of the TC pins must be used for multiple EP016 divider chains.
Load CLK
1001 0000
1001 0001 1111 1100 *** ***
1111 1101
1111 1110
1111 1111
Load
PE *** TC DIVIDE BY 113
Figure 5. Divide by 113 EP016 Programmable Divider Waveforms
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MC10EP016, MC100EP016 Applications Information (continued)
EP01
Q0 to Q7 CE EP016 LSB CLK CLK PE
Q0 to Q7 CE PE EP016
Q0 to Q7 CE EP016 PE
Q0 to Q7 CE EP016 MSB CLK CLK
EP01
LO
PE
TC
CLK CLK
TC
EP01
CLK CLK
TC
TC
P0 to P7
P0 to P7
P0 to P7
P0 to P7
CLK CLK
Figure 6. 32-Bit Cascaded EP016 Programmable Divider
Figure 6 shows a typical block diagram of a 32-bit divider chain. Once again to maximize the frequency of operation EP01 OR gates were used. For lower frequency applications a slower OR gate could replace the EP01. Note that for a 16-bit divider the OR function feeding the PE (program enable) input CANNOT be replaced by a wire OR tie as the TC output of the least significant EP016 must also feed the CE input of the most significant EP016. If the two TC outputs were OR tied the cascaded count operation would not operate properly. Because in the cascaded form the PE feedback is external and requires external gating, the maximum frequency of operation will be significantly less than the same operation in a single device.
Maximizing EP016 Count Frequency The EP016 device produces 9 fast transitioning single-ended outputs, thus VCC noise can become significant in situations where all of the outputs switch simultaneously in the same direction. This VCC noise can negatively impact the maximum frequency of operation of the device. Since the device does not need to have the Q outputs terminated to count properly, it is recommended that if the outputs are not going to be used in the rest of the system they should be left unterminated. In addition, if only a subset of the Q outputs are used in the system only those outputs should be terminated. Not terminating the unused outputs will not only cut down the VCC noise generated but will also save in total system power dissipation. Following these guidelines will allow designers to either be more aggressive in their designs or provide them with an extra margin to the published data book specifications.
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MC10EP016, MC100EP016
Q Driver Device Q 50 W 50 W
D Receiver Device D
VTT VTT = VCC - 2.0 V
Figure 7. Typical Termination for Output Driver and Device Evaluation (See Application Note AND8020 - Termination of ECL Logic Devices.)
Resource Reference of Application Notes
AN1404 AN1405 AN1406 AN1504 AN1568 AN1650 AN1672 AND8001 AND8002 AND8009 AND8020
- - - - - - - - - - -
ECLinPS Circuit Performance at Non-Standard VIH Levels ECL Clock Distribution Techniques Designing with PECL (ECL at +5.0 V) Metastability and the ECLinPS Family Interfacing Between LVDS and ECL Using Wire-OR Ties in ECLinPS Designs The ECL Translator Guide Odd Number Counters Design Marking and Date Codes ECLinPS Plus Spice I/O Model Kit Termination of ECL Logic Devices
For an updated list of Application Notes, please see our website at http://onsemi.com.
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MC10EP016, MC100EP016
PACKAGE DIMENSIONS
LQFP FA SUFFIX 32-LEAD PLASTIC PACKAGE CASE 873A-02 ISSUE A
A
32 4X 25
A1
0.20 (0.008) AB T-U Z
1
-T- B B1
8
-U- V P DETAIL Y
17
AE
V1 AE DETAIL Y
9
-Z- 9 S1 S
4X
0.20 (0.008) AC T-U Z
G -AB-
SEATING PLANE
DETAIL AD
-AC-
BASE METAL
F
8X
M_ R
CE
SECTION AE-AE
X DETAIL AD
GAUGE PLANE
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0.250 (0.010)
H
W
K
Q_
EE EE EE EE
N
D
0.20 (0.008)
M
AC T-U Z
0.10 (0.004) AC
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DATUM PLANE -AB- IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DATUMS -T-, -U-, AND -Z- TO BE DETERMINED AT DATUM PLANE -AB-. 5. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE -AC-. 6. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.250 (0.010) PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE -AB-. 7. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. DAMBAR PROTRUSION SHALL NOT CAUSE THE D DIMENSION TO EXCEED 0.520 (0.020). 8. MINIMUM SOLDER PLATE THICKNESS SHALL BE 0.0076 (0.0003). 9. EXACT SHAPE OF EACH CORNER MAY VARY FROM DEPICTION. MILLIMETERS MIN MAX 7.000 BSC 3.500 BSC 7.000 BSC 3.500 BSC 1.400 1.600 0.300 0.450 1.350 1.450 0.300 0.400 0.800 BSC 0.050 0.150 0.090 0.200 0.500 0.700 12_ REF 0.090 0.160 0.400 BSC 1_ 5_ 0.150 0.250 9.000 BSC 4.500 BSC 9.000 BSC 4.500 BSC 0.200 REF 1.000 REF INCHES MIN MAX 0.276 BSC 0.138 BSC 0.276 BSC 0.138 BSC 0.055 0.063 0.012 0.018 0.053 0.057 0.012 0.016 0.031 BSC 0.002 0.006 0.004 0.008 0.020 0.028 12_ REF 0.004 0.006 0.016 BSC 1_ 5_ 0.006 0.010 0.354 BSC 0.177 BSC 0.354 BSC 0.177 BSC 0.008 REF 0.039 REF
J
DIM A A1 B B1 C D E F G H J K M N P Q R S S1 V V1 W X
-T-, -U-, -Z-
MC10EP016, MC100EP016
ECLinPS is a trademark of Semiconductor Components Industries, LLC (SCILLC).
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.
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